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ASAHI KASEI
[AK93C45C/55C/65C]
AK93C45C/55C/65C
1K/2K/4Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION : VCC = 1.5V to 5.5V(READ) VCC = 1.6V to 5.5V(WRITE/WRAL/PAGE WRITE) AK93C45C 1024 bits, 64 x 16 organization AK93C55C 2048 bits, 128 x 16 organization AK93C65C 4096 bits, 256 x 16 organization SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors -1.0MHz(1.5VVCC<2.5V), 4.0MHz(2.5VVCC5.5V) LOW POWER CONSUMPTION - 0.8A Max. Standby High Reliability - Endurance : 1000K E/W cycles / Address - Data Retention : 10 years Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE Busy/Ready status signal Software and Hardware controlled write protection IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package (TMSOP, SON, USON)
DO
DATA REGISTER
16 16
DI
INSTRUCTION REGISTER
R/W AMPS AND AUTO ERASE
INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION
EEPROM
93C45C=1024bit 93C55C=2048bit 93C65C=4096bit
ADD. BUFFERS
DECODER
CS
VPP SW
SK
PE
VREF
VPP GENERATOR
Block Diagram
DAM06E-01 -12005/10
ASAHI KASEI
[AK93C45C/55C/65C]
General Description
The AK93C45C/55C/65C is a 1024/2048/4096-bit serial CMOS EEPROM divided into 64/128/256 registers of 16 bits each. The AK93C45C/55C/65C has 6 instructions such as READ, WRITE, PAGE WRITE, EWEN, EWDS and WRAL. Those instructions control the AK93C45C/55C/65C. The AK93C45C/55C/65C can operate full function under wide operating voltage range. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C45C/55C/65C, consisting of chip select (CS), serial clock (SK), data-in (DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C45C/55C/65C takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C45C/55C/65C takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output.
Software controlled write protection When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction is disabled. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE, PAGE WRITE, WRAL, EWEN and EWDS instructions.
Busy/Ready status signal After a WRITE, PAGE WRITE, WRAL instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of `tCS'. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
DAM06E-01 -2-
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
Type of Products Model AK93C45CT AK93C45CL AK93C45CU AK93C55CT AK93C55CL AK93C55CU AK93C65CT AK93C65CL AK93C65CU Memory size 1K bits Temp. Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C VCC 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V Package 8pin Plastic TMSOP 8pin Plastic SON 8pin Plastic USON 8pin Plastic TMSOP 8pin Plastic SON 8pin Plastic USON 8pin Plastic TMSOP 8pin Plastic SON 8pin Plastic USON
2K bits
4K bits
Pin Arrangement
AK93C45CT/55CT/65CT
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC PE GND
AK93C45CL/55CL/65CL
VCC NC PE GND 1 2 3 4 8 7 6 5 CS SK DI DO
8pin TMSOP
8pin SON
AK93C45CU/55CU/65CU
VCC NC PE GND
1 2 3 4 8 7 6 5
CS SK DI DO
8pin USON
Pin Name CS SK DI DO PE VCC GND NC
*1: Please Open NC pin. DAM06E-01
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Program Enable Power Supply Ground Not Connected
*1
(note) The PE is internally pulled up to VCC ( R = typ.2.5M, VCC=5V ).
2005/10 -3-
ASAHI KASEI
[AK93C45C/55C/65C]
Functional Description
The AK93C45C/55C/65C has 6 instructions such as READ, WRITE, PAGE WRITE, EWEN, EWDS and WRAL. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address location. The CS pin must be brought low for a minimum of `tCS' between each instruction when the instruction is continuously executed.
Instruction
Start Op Bit Code READ 1 10 WRITE 1 01 PAGE WRITE 1 11 EWEN 1 00 EWDS 1 00 WRAL 1 00
Address A5-A0 A5-A0 A5-A0 11XXXX 00XXXX 010000
Data D15-D0 D15-D0 D15-D0
Writes register.
Comments
Reads data stored in memory, at specified address. Page Write register. Write enable must precede all programming modes. Disables all programming instructions.
D15-D0
Writes all registers.
X: Don't care table1. Instruction Set for the AK93C45C Start Op Bit Code READ 1 10 WRITE 1 01 PAGE WRITE 1 11 EWEN 1 00 EWDS 1 00 WRAL 1 00
Instruction
Address XA6-A0 XA6-A0 XA6-A0 11XXXXXX 00XXXXXX 010000000
Data D15-D0 D15-D0 D15-D0
Writes register.
Comments
Reads data stored in memory, at specified address. Page Write register. Write enable must precede all programming modes. Disables all programming instructions.
D15-D0
Writes all registers.
X: Don't care table2. Instruction Set for the AK93C55C Start Op Bit Code READ 1 10 WRITE 1 01 PAGE WRITE 1 11 EWEN 1 00 EWDS 1 00 WRAL 1 00
Instruction
Address A7-A0 A7-A0 A7-A0 11XXXXXX 00XXXXXX 010000000
Data D15-D0 D15-D0 D15-D0
Writes register.
Comments
Reads data stored in memory, at specified address. Page Write register. Write enable must precede all programming modes. Disables all programming instructions.
D15-D0
Writes all registers.
X: Don't care table3. Instruction Set for the AK93C65C (Note) The AK93C45C/55C/65C perceives the start bit in the logic"1" and also "01".
DAM06E-01 -4-
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of `tCS'. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
PE CS SK DI DO
0 0 1 1 0 2 1 3 4 A5 5 A4 8 A1 9 A0 10 D15 11 D14 23 D2 24 D1 25 D0 tCS
Start Bit
Op code
Hi-Z
Busy Ready tE/W
AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
WRITE (AK93C45C)
PE CS SK DI DO
0 0 1 1 0 2 1 3 X 4 5 A6 10 A1 11 A0 12 D15 13 D14 25 D2 26 D1 27 D0 tCS
Start Bit
Op code
Hi-Z
Busy Ready tE/W X: Don't care
AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
WRITE (AK93C55C)
PE CS SK DI DO
0 0 1 1 0 2 1 3 4 A7 5 A6 10 A1 11 A0 12 D15 13 D14 25 D2 26 D1 27 D0 tCS
Start Bit
Op code
Hi-Z
Busy Ready tE/W
AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
WRITE (AK93C65C)
DAM06E-01 -52005/10
ASAHI KASEI
[AK93C45C/55C/65C]
PAGE WRITE
AK93C45C/55C/65C has Page Write mode, which can write the data within 4 words with one programming cycle. The input data sent to the shift register within 4 words. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of `tCS'. After the receipt of each word, the two lower order address pointer bits internally incremented by one. The higher order six bits of the word address remains constant. When the highest address is reached "XXXX XX11", the address counter rolls over to address "XXXX XX00" allowing the page write cycle to be continued indefinitely. If AK93C45C/55C/65C is transmitted more than 4 words, the address counter will "roll over" and the previously written data will be overwritten. When AK93C45C/55C/65C is transmitted 6 words, fifth word will be overwritten to first word, and sixth word will be overwritten to second word. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
PE CS SK
0 1 2 3 4 5 6 7 8 9 10 11 12 23 24 25
Data(n) DI DO 0 1 1 1 A5 A4 A3 A2
Hi-Z
A1
A0
D15 D14 D13
D2
D1
D0
AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
PE CS SK
26 27 39 40 41
tCS
Data(n+3) D15
Hi-Z
Data(n+1) DI DO D15 D14 D2 D1 D0 D0 D15 D14
D2
D1
D0 Busy tE/W Ready
PAGE WRITE (AK93C45C)
DAM06E-01 -6-
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
PE CS SK
0 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27
Data(n) DI DO 0 1 1 1 X A6 A5 A4
Hi-Z
A3
A2
A1
A0
D15
D2
D1
D0
AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
PE CS SK
28 29 41 42 43
tCS
Data(n+3) D15
Hi-Z
Data(n+1) DI DO D15 D14 D2 D1 D0 D0 D15 D14
D2
D1
D0 Busy tE/W Ready
X: Don't care
PAGE WRITE (AK93C55C)
PE CS SK
0 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27
Data(n) DI DO 0 1 1 1 A7 A6 A5 A4
Hi-Z
A3
A2
A1
A0
D15
D2
D1
D0
AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
PE CS SK
28 29 41 42 43
tCS
Data(n+3) D15
Hi-Z
Data(n+1) DI DO D15 D14 D2 D1 D0 D0 D15 D14
D2
D1
D0 Busy tE/W Ready
PAGE WRITE (AK93C65C)
DAM06E-01 -7-
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
WRAL
The write instruction is followed by 16 bits of data to be written into all address. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of `tCS'. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
PE CS SK DI DO
0 0 1 1 0 2 0 3 0 4 1 5 0 6 0 7 0 8 0 9 10 D15 11 D14 12 D13 13 D12 25 D0 tCS
Start Bit
Hi-Z
Busy R eady tE/W
AK93C45C output a logic "1" (R eady status), if previous instruction is W RITE, PAGE W RITE, W RAL.
WRAL (AK93C45C)
PE CS SK DI DO
0 0 1 1 0 2 0 3 0 4 1 5 0 6 0 7 0 8 0 9 0 10 0 11 12 D15 13 D14 27 D0 tCS
Start Bit
Hi-Z
Busy R eady tE/W
AK93C55C output a logic "1" (R eady status), if previous instruction is W RITE, PAGE W RITE, W RAL.
WRAL (AK93C55C)
PE CS SK DI DO
0 0 1 1 0 2 0 3 0 4 1 5 0 6 0 7 0 8 0 9 0 10 0 11 12 D15 13 D14 27 D0 tCS
Start Bit
Hi-Z
Busy R eady tE/W
AK93C65C output a logic "1" (R eady status), if previous instruction is W RITE, PAGE W RITE, W RAL.
WRAL (AK93C65C)
DAM06E-01 -8-
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
READ
The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. When the highest address is reached, the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely.
CS SK DI DO
0 0 1 1 1 2 0 3 4 A5 5 A4 8 A1 9 A0 10 11 25 26 40 41
Start bit
Op code
Hi-Z
AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
D15 D14 D0 0 Dummy address[A5-A0] Bit
D15
D1
D0
address[A5-A0]+1
READ (AK93C45C)
CS SK DI DO
0 0 1 1 1 2 0 3 X 4 5 A6 10 A1 11 A0 12 13 27 28 42 43
Start bit
Op code
Hi-Z
AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
D15 D14 D0 0 Dummy address[A6-A0] Bit
D15
D1
D0
address[A6-A0]+1 X: Don't care
READ (AK93C55C)
CS SK DI DO
0 0 1 1 1 2 0 3 4 A7 5 A6 10 A1 11 A0 12 13 27 28 42 43
Start bit
Op code
Hi-Z
AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
D15 D14 D0 0 Dummy address[A7-A0] Bit
D15
D1
D0
address[A7-A0]+1
READ (AK93C65C)
DAM06E-01 -92005/10
ASAHI KASEI
[AK93C45C/55C/65C]
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction is disable. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions.
PE CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
Start bit
AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE PAGE WRITE, WRAL.
X: Don't care
EWEN / EWDS (AK93C45C)
PE CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
10 X
11 X
Start bit
AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE PAGE WRITE, WRAL.
X: Don't care
EWEN / EWDS (AK93C55C)
PE CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
10 X
11 X
Start bit
AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE PAGE WRITE, WRAL.
X: Don't care
EWEN / EWDS (AK93C65C)
DAM06E-01 - 10 2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
Absolute Maximum Ratings
Parameter Power Supply All Input Voltages with Respect to Ground Ambient storage temperature Symbol VCC VIO Tst Min -0.6 -0.6 -65 Max +6.5 VCC+0.6 +150 Unit V V
C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Power Supply 1(Except READ) Power Supply 2(READ) Ambient Operating Temperature Symbol VCC1 VCC2 Ta Min 1.6 1.5 -40 Max 5.5 5.5 +85 Unit V V C
DAM06E-01 - 11 -
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS ( 1.5V VCC 5.5V, -40C Ta 85C, unless otherwise specified ) Parameter Current Dissipation (WRITE) Current Dissipation (WRAL) Current Dissipation (READ) Current Dissipation (Standby) Input High Voltage Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICCSB VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH1 VOH2 VOH3 Output Low Voltage VOL1 VOL2 VOL3 Input Leakage Output Leakage ILI ILO Condition VCC=5.5V, tSKP=250ns, *1 VCC=1.8V, tSKP=1.0s, *1 VCC=5.5V, tSKP=250ns, *1 VCC=1.8V, tSKP=1.0s, *1 VCC=5.5V, tSKP=250ns, *1 VCC=1.5V, tSKP=1.0s, *1 VCC=5.5V VCC=5.0V10% 2.5V VCC 5.5V 1.5V VCC < 2.5V VCC=5.0V10% 1.8V VCC 5.5V 1.5V VCC < 1.8V VCC=5.0V10% IOH=-0.4mA 2.5V VCC 5.5V IOH=-0.1mA 1.5V VCC < 2.5V IOH=-0.1mA VCC=5.0V10% IOL=1.5mA 2.5V VCC 5.5V IOL=1.0mA 1.5V VCC < 2.5V IOL=0.1mA VCC=5.5V, VIN=5.5V VCC=5.5V, VOUT=5.5V, CS=GND *3 *2 2.0 0.8 x VCC 0.8 x VCC -0.1 -0.1 -0.1 2.2 0.8 x VCC 0.8 x VCC 0.4 0.4 0.4
1.0 1.0
Min.
Max. 2.5 1.5 2.5 1.5 1.5 0.1 0.8 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.8 0.15 x VCC 0.1 x VCC
Unit mA mA mA mA mA mA
A
V V V V V V V V V V V V
A A
*1 : VIN=VIH/VIL, DO=Open *2 : VIN=VCC/GND, CS=GND, DO=Open, PE=VCC/Open *3 : CS, SK, DI pin
DAM06E-01 - 12 -
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
(2) A.C. ELECTRICAL CHARACTERISTICS ( 1.5V VCC 5.5V, -40C Ta 85C, unless otherwise specified ) Parameter SK Cycle Time SK Pulse Width Symbol tSKP1 tSKP2 tSKW1 tSKW2 CS Setup Time CS Hold Time Data Setup Time Data Hold Time Output delay *4 tCSS1 tCSS2 tCSH tDIS1 tDIS2 tDIH1 tDIH2 tPD1 tPD2 Selftimed Programming Time Min CS Low Time SK HOLD Time CS to Status Valid CS to Output High-Z tE/W tCS1 tCS2 tCCH1 tCCH2 tSV1 tSV2 tOZ1 tOZ2 Endurance *5 2.5V VCC 5.5V 1.5V VCC < 2.5V 2.5V VCC 5.5V 1.5V VCC < 2.5V 2.5V VCC 5.5V 1.5V VCC < 2.5V 1.6V VCC 5.5V 2.5V VCC 5.5V 1.5V VCC < 2.5V 2.5V VCC 5.5V 1.5V VCC < 2.5V 2.5V VCC 5.5V 1.6V VCC < 2.5V 2.5V VCC 5.5V 1.5V VCC < 2.5V 5.5V, 25C, PAGE WRITE 1,000,000 60 200 60 200 125 300 75 100 Condition 2.5V VCC 5.5V 1.5V VCC < 2.5V 2.5V VCC 5.5V 1.5V VCC < 2.5V 2.5V VCC 5.5V 1.5V VCC < 2.5V Min. 250 1.0 100 400 80 200 0 50 100 50 100 60 300 5 Max. Unit ns
s
ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns
E/W cycles/ Address
*4 : CL=100pF *5 : This parameter is not tested to all samples.
DAM06E-01 - 13 -
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
Synchronous Data timing
CS
tCSS tSKW tSKW tSKP
SK
tDIS tDIH
DI
tSV
0
1
DO
Hi-Z
AK93C45C/55C/65C output a logical "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL.
The Start of Instruction
CS
tCSH
SK DI
tPD tPD tPD tOZ
DO
D3
D2
D1
D0
Hi-Z
The End of Instruction
DAM06E-01 - 14 -
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
tCS
CS
tCSH tCCH
SK
tDIS tDIH
DI DO
D1
D0
tSV Hi-Z Busy Ready
tE/W
Busy/Ready Signal Output
DAM06E-01 - 15 -
2005/10
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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